We're looking for an experienced chip designer with a strong full-stack software + ML skillset to build the co-pilot for chip designers with us. You will be pushing and productizing the frontier of EDA tools & ML techniques to enable our novel use cases.

As our Founding R&D Engineer, you will be working directly with our CTO to co-own, architect, and ship co-pilot software enabling functional correctness convergence and PPA optimization in RTL design. You will also be working directly with our world-class customers building advanced chips and IP to understand their needs and iterate on our product with real feedback.

Minimum requirements:

• 1+ tapeouts with experience across the RTL2GDS + verification flows with commercial tools
• Significant R&D experience devising new software techniques leveraging statistics & AI/ML methods
• Good at shipping high-quality code quickly
• Passionate about chips and building new software to help chip designers around the world
• Resilient, data-driven, and works from first principles

Ideal requirements:

• Significant experience with PPA optimization and/or functional correctness convergence
• Multiple chip tapeouts that include advanced technology nodes
• PhD in Electrical Engineering (VLSI) or equivalent work/research experience

Apply to chat with us about the role in more detail!

Note that this is an in-person role in the SF Bay Area.